EDS Model Generator converts VHDL source file to a simulatable component in EDSpice, the SPICE based simulator (which is a plug-in). This also serves the purpose of making simulation much faster.

Since VHDL can only be used to create digital models, only digital simulation models can be created using EDSpice Simulation Model Generator. Earlier, knowledge of programming was essential for writing digital models. It would be much easier for an electronic engineer to create the models using VHDL rather than learn other nonstandard programming languages for creating models. Therefore a need for developing a tool arose which could convert VHDL models to SPICE models.

Note: EDComX is a tool which can be used for creating both analog and digital models, however it assumes programming knowledge and the user has to build his own simulation SPICE Model.

Invoking EDSpice Simulation Model Generator

• Select EDSpice Simulation Model Generator from the tasklist or task toolbar of the Project Explorer.
• Select EDSpice Simulation Model Generator from the floating menu that appears on right clicking System menu in Project Explorer.

A window titled Model Generator for EDSpice Simulator appears

Operation

Double click once in the cell next to VHDL Source File name and an ellipsis will appear. Click on it to select the file. As soon as the file is selected, EDSpice Generator will compile the VHDL file and exhibit the results in File Viewer windows. The errors in the VHDL file (if any) have to be corrected before proceeding. Once the VHDL file is error free, the focus automatically moves to the Model Project window.

Generating models for a wrs file

1. EDWinXP → Project Explorer →System →EDS Model generator
2. Model name → Give a proper model name
3. Source Netlist file →Select appropriate Netlist file
4. MM function description →Give a description
5. Click on Build
6. This will create a special part in the MMMGEN.PART in the library explorer, which can be used as simulatable components.