EDSpice Simulation Model Generator

This tool converts a VHDL source file to a simulatable component in EDSpice, the SPICE based simulator ( which is a plug-in). This also serves the purpose of making simulation much faster Since VHDL can only be used to create digital models, only digital simulation models can be created using EDSpice Simulation Model Generator. Earlier, knowledge of programming was essential for writing digital models. It would be much easier for an electronic engineer to create the models using VHDL rather than learn other non-standard programming languages for creating models. Therefore a need for developing a tool arose which could convert VHDL models to SPICE models.

Starting EDSpice Simulation Model Generator

1. Select EDSpice Simulation Model Generator from the tasklist or task toolbar of the Project Explorer.
OR 1. Select EDSpice Simulation Model Generator from the floating menu that appears on right clicking System menu in Project Explorer.
2. A window titled Model Generator for EDSpice Simulator appears.The opening window of EDSpice Simulation Model Generator is as shown below.

3. Double click once in the cell next to VHDL Source File name and an ellipsis will appear. Click it to select the file.
4. As soon as the file is selected, EDSpice Generator will compile the VHDL file and exhibit the results in File Viewer windows. The errors in the VHDL file (if any) have to be corrected before proceeding. Once the VHDL file is error free, the focus automatically moves to the Model Project window.

The Model Project window is shown in the picture below.

5. Now values of Global Parameters can be entered. Global Parameters window is shown below.

6. On clicking Add Parameters, a dialog titled Set Global Parameter appears.

7. Select a value from the dropdown list for Function, Transition, Control net and Test net, enter a value for Timing and then press Apply.

8. Once parameters are entered, the menu items Remove Parameter and Remove all parameters become active in the Global Parameters window.

9. Once the global parameters are set, the parameters for the individual gates may also be set.

10. Once Gate parameters are set, press the Build button to compile the dll. If you would like to make more changes to your model, the Visual C++ source files contained in the Output Path can be edited. After editing the files, compile the dll and copy it to the \Eds_cml folder.

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