VHDL Editor is basically an editor for writing VHDL source files. Its working is very much similar to any normal programming editor. All keywords present in the source are highlighted in blue. The source code may be compiled and error messages displayed to help quick debugging.
This module may be invoked from Project Explorer in the following ways.
1. Right click System and select VHDL Editor from the list.
OR
2. Select VHDL Editor from the Tasklist or from the Task toolbar.

Note: By default, the task toolbar will not be displayed. It may be enabled from View menu in the Project Explorer.
The VHDL Editor appears as shown below:

Build

Compile
Compiles the *.vhdl source file and generates the *.wrs file.Enable this menu item from Build menu to compile the vhdl source file and generate wirelist file (*.wrs). Compilation stops at the first occurrence of error and the error message gets displayed in the output window. Double click on the message to highlight the line in red within the code. The display of compile errors may be switched off either from the menu Edit | Switch Off Compile Errors or by double clicking the message in the output window. The output window may be made visible from the menu View | Output. Compile & Import Compiles the *.vhdl source file, generates the *.wrs file and imports it to the project.Select this menu item from Build menu. The compiled output file (*.wrs file) gets loaded in Netlist/Wirelist Export & Import dialog.

Create MM Model
Opens the Mixed Mode Simulation Model Generator, which helps to generate a simulateable model.Select this menu item from Build menu. The *.vhdl source file is compiled and the output file (*.wrs file) gets loaded in Mixed Mode Simulation Model Generator.

Create EDSpice Model
Opens the EDSpice Simulation Model Generator, which helps to generate a simulateable model in EDSpice.Select this menu item from Build menu. The *.vhdl source file is compiled and the output file (*.wrs file) gets loaded in EDSpice Simulation Model Generator.

Create Xilinx Output
Opens Netlist/Wirelist Export & Import utility to convert the compiled vhdl output file (*.wrs) to Xilinx netlist format. Select this menu item from Build menu. The *.vhdl source file is compiled and the output file (*.wrs file) gets loaded in Netlist/Wirelist Export & Import dialog.

Create CUPL Output
Opens Netlist/Wirelist Export & Import utility to convert the compiled vhdl output file (*.wrs) to CUPL netlist format. Select this menu item from Build menu. The *.vhdl source file is compiled and the output file (*.wrs file) gets loaded in Netlist/Wirelist Export & Import dialog.

Create JEDEC Output
Opens Netlist/Wirelist Export & Import utility to convert the compiled vhdl output file (*.wrs) to JEDEC netlist format. Select this menu item from Build menu. The *.vhdl source file is compiled and the output file (*.wrs file) gets loaded in Netlist/Wirelist Export & Import dialog.