VHDL Editor

VHDL Editor is very much similar to any other programming editor and is used for coding VHDL source files. All keywords present in the source are highlighted in blue. The source code may be compiled and error messages are displayed for quick debugging.

Invoking VHDL Editor

This module is invoked from Project Explorer in the following ways.

*Right click System and select VHDL Editor from the list.
*Select VHDL Editor from the Tasklist or from the Task toolbar.

Note: By default, the task toolbar is not displayed. It may be enabled from View menu in the Project Explorer.

The VHDL Editor appears as shown below:

Some main features of VHDL Editor are:

1. It compiles the source file and generates wirelist (*.wrs) output file.
2. The output file (*.wrs) may be imported directly to the system.
3. It helps to generate simulateable models in Mixed Mode & EDSpice Model Generators.
4. Helps to convert the (*.wrs) file to Xilinx, CUPL and JEDEC formats.

The code is written in the workspace and is compiled using Build → Compile (F7). Any circuit can be import to EDWinXP by using Build → Compile and Import.

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Invoking VHDL Editor

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