Comparator_3_bit
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee, std;
use ieee.std_logic_1164.all;
use std.numeric_std.all;
entity comp is
port (a, b : in signed(2 downto 0);
eq, eqi, gt, lt : out boolean);
end entity comp;
architecture behave of comp is
begin
process (a, b)
begin
eq <= a = b;
eqi <= a /= b;
gt <= a > b;
lt <= a < b;
end process;
end behave;
