adder_4_bit
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Open Schematic Editor,Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.numeric_std.all;
use work.user_package.all;
entity adder is
port (ce : in std_logic;
a, b : in unsigned15;
s : out unsigned15);
end adder;
architecture adder_a of adder is
begin
process (a, b, ce)
begin
if ce = '1' then
s <= a + b;
end if;
end process;
end adder_a;
