Binary BCD Converter
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee, std, work;
use ieee.std_logic_1164.all;
use std.numeric_std.all;
use work.user_package.all;
entity binbcd is
port (ce : in std_logic;
inpt : in unsigned15;
otpt1 : out unsigned15;
otpt2 : out bit);
end binbcd;
architecture binbcd_a of binbcd is
begin
process (ce, inpt)
begin
if ce = '1' then
if inpt <= 9 then
otpt1 <= inpt;
otpt2 <= '0';
else
otpt2 <= '1';
if inpt = 10 then
otpt1 <= 0;
elsif inpt = 11 then
otpt1 <= 1;
elsif inpt = 12 then
otpt1 <= 2;
elsif inpt = 13 then
otpt1 <= 3;
elsif inpt = 14 then
otpt1 <= 4;
elsif inpt = 15 then
otpt1 <= 5;
end if;
end if;
end if;
end process;
end binbcd_a;
