Decade Counter
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity counter2 is
port(clk,rst : in std_logic;
count : out unsigned(3 downto 0));
end counter2;
architecture counter2_bhv of counter2 is
signal reg : unsigned(3 downto 0);
begin
process(clk,rst)
begin
if rst='1' or reg="1010" then
reg <= "0000";
elsif (clk'EVENT) and (clk='1') then
reg <= reg + "0001";
end if;
end process;
count <= reg;
end counter2_bhv;
