Johnson Counter
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Johnsons_counter is
port(clk : in std_logic;
count : out std_logic_vector(7 downto 0));
end Johnsons_counter;
architecture beh of Johnsons_counter is
signal q : std_logic_vector(7 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
q(7) <= q(6);
q(6) <= q(5);
q(5) <= q(4);
q(4) <= q(3);
q(3) <= q(2);
q(2) <= q(1);
q(1) <= q(0);
q(0) <= not q(7)
end if;
end process;
count <= q;
end beh;
