16X8 ROM
- Right Click on System from Project Explorer and select VHDL Editor from the List
- Enter the following code in the workspace provided in the VHDL Editor window
- Save the file (.vhd) and compile the code using Compile & Import option from Build menu.It compiles the source file and generates wirelist (*.wrs) output file
- Output window shows the status of errors
- Click on Import button in Netlist/Wirelist Export&Import window.
- Open Schematic Editor,Autoplace the components by selecting Tools|Autoplace.
- Autoconnect the components by selecting menu Tools|Connections.Select option tool Autconnect all wires from Connect components
- Pcb layout creation is not possible for a schematic using vhdl as its component part includes only symbol hence couldn't pack components.
library ieee;
use ieee.std_logic_1164.all;
entity rom is
port (ce, oe : in std_logic;
addr : in std_logic_vector(3 downto 0);
q : out std_logic_vector(7 downto 0));
end rom;
architecture rom_a of rom is
begin
process (ce, oe, addr)
begin
if (ce = '1') and (oe = '1') then
case inpt is
when "0000" => q <= "00000001";
when "0001" => q <= "00000010";
when "0010" => q <= "00000100";
when "0011" => q <= "00001000";
when "0100" => q <= "00010000";
when "0101" => q <= "00100000";
when "0110" => q <= "01000000";
when "0111" => q <= "10000000";
when "1000" => q <= "00000001";
when "1001" => q <= "00000010";
when "1010" => q <= "00000100";
when "1011" => q <= "00001000";
when "1100" => q <= "00010000";
when "1101" => q <= "00100000";
when "1110" => q <= "01000000";
when "1111" => q <= "10000000";
when others => q <= null;
end case;
else
q <= "ZZZZZZZZ";
end if;
end process;
end rom_a;
